1. Field of the Invention
The present invention relates generally to electrically programmable and erasable memory, and more particularly, to methods and devices for increasing a memory operation window and reducing a second bit effect in multi-bit-per-cell operations.
2. Description of Related Art
Electrically programmable and erasable nonvolatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a nonvolatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
Charge trapping memory devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of a charge trapping memory flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology keeps scaling down.
A traditional floating gate device stores 1 bit of charge in a conductive floating gate. The advent of charge trapping memory cells provides the ability to store 2 bits of flash cells in an Oxide-Nitride-Oxide (ONO) dielectric. In a typical structure of a charge trapping memory cell, a nitride layer is used as a trapping material positioned between a top oxide layer and a bottom oxide layer. The charge in the ONO dielectric with a nitride layer may be trapped on either the left side or the right side of a charge trapping memory cell. The interaction of the left bit and the right bit, also known as a second bit effect, limits a voltage threshold window between programmed and erased states. The second bit effect consequently affects the size of an operation window, which in turn potentially caps the scalability on the number of bits in the charge trapping memory cells. Therefore, it is desirable to have methods and devices that reduce the second bit effect and thereby increase a memory operation window in a charge trapping memory.